1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a new structure for a semiconductor memory device, wherein two or more groups of bit line pairs are disposed for memory cells arranged in columns, wherein the bit line pairs are prevented from operating in error as a result of noise.
2. Description of the Related Art
Semiconductor memory device, which randomly access SRAM or DRAM and read or write data at high speeds, are used as memory in computers requiring high speed cache memory. Also, SRAM or the like are formed in system LSI chips which constitute microprocessors.
Dual port RAM was developed in order to realize high speeds. In dual port RAM, two groups of bit line pairs are established for each of the memory cells arranged in columns. This memory has a first bit line pair for carrying out reading and writing, for example, and also a second bit line pair which can carry out reading. While reading with one bit line pair, the memory can use the other bit line pair for writing. Or, while reading data in a memory cell by means of one bit line pair, the memory can read data in another memory cell using the other bit line air.
FIG. 9 is a diagram of a conventional semiconductor memory apparatus. In the semiconductor memory apparatus shown in FIG. 9, only one memory cell MC is shown for purposes of convenience, but usually a plurality of memory cells MC is arranged in columns and words. Two bit line pairs, BLA, XBLA and BLB, XBLB, are arranged in columns. The bit line XBLA forms one pair with the bit line BLA and has a signal which is the reverse of the bit line BLA. Also, two word lines WLA and WLB are disposed in words. When the word line WLA is selected, the bit line pair BLA, XBLA is connected to the memory cell MC; when the word line WLB is selected, the bit line pair BLB, XBLB is connected to the memory cell MC.
The bit line pair BLA, XBLA is connected to the data bus line pair DBA, XDBA by means of the column selection circuit CLSA. A write amp WA and sense amp SAA are established on the data bus line pair DBA, XDBA and connected to the output buffer OBA. Also, the bit line pair BLB, XBLB is connected to the data bus line pair DBB, XDBB by means of the column selection circuit CLSB. A sense amp SAB is established on the data bus line pair DBB, XDBB and connected to the output buffer OBB.
In this way, the dual port structure, having two groups of bit line pairs and data bus line pairs connected thereto, makes possible the following, for example. While data are written from one data bus line pair DBA, XDBA by means of the first bit line pair BLA, XBLA, data can be read from the second bit line pair BLB, XBLB by means of the second data bus line pair DBB, XDBB. Furthermore, it is also possible to read two memory cells at the same time using both bit line pairs.
In data reading, the bit line pair and data bus line pair are driven by the memory cell MC; small potential difference generated by the data bus line pair is detected and amplified by the sense amp. Meanwhile, in data writing, the writing amp drives the data bus line pair and bit line pair and forces a reversal of the memory cell state. In order to have a high capacity memory, the memory cell driving power is kept to a minimum, while the driving power of the writing amp is made greater than that of the memory cell.
A further increase of the number of bit line pairs can make the aforementioned dual port RAM into multi-port RAM structure with three or more ports.
However, because the aforementioned dual port RAM has the two groups of bit line pairs juxtaposed in columns, the signal of one bit line pair influences the other bit line pair by means of parasitic capacity C0, C1. Increased capacity of memory results in longer bit line pairs and the aforementioned parasitic capacity becomes large as well. Consequently, crosstalk between the bit line pairs increases.
The following problem may result especially when a read operation is performed using the second bit line pair BLB, XBLB. When the write operation is carried out with the first bit line pair BLA, XBLA to another memory in the same column, the change in the potential of the first bit line pair BLA, XBLA, which is driven with a large amplitude, is transferred by means of the parasitic capacity to the second bit line pair BLB, XBLB, which is driven with a small amplitude. This can cause errors in the read operation carried out with the second bit line pair.
FIG. 10 is a cross sectional view showing an example of the signal wiring layer for the two groups of bit line pairs. The bit lines BLA and BLB, disposed on the left side of the memory cell MC, are coupled by means of the parasitic capacity C1. Likewise, the bit lines XBLA and XBLB, disposed on the right side of the memory cell MC, are coupled by means of the parasitic capacity C0. In that case, the second bit line pair BLB, XBLB, which is engaged in the read operation, is driven at the high, low level by the memory cell MC, while the first bit line pair BLA, XBLA, which is engaged in the write operation, is driven at the low, high level by the write amp WA. Whereupon, the low, high level of the first bit line pair BLA, XBLA, which is driven at a greater amplitude, is transferred to the second bit line pair BLB, XBLB by means of the parasitic capacitors C0, C1. Then, the level of the second bit line pair BLB, XBLB, which is driven at a lower amplitude, is sometimes put in the reverse state.
FIG. 11 is an example of a signal waveform diagram showing the operation of the Prior art. In FIG. 11, the preset signal PRA, PRB, not shown in FIG. 9, reach the high level so that the bit line pairs and data bus line pairs are all preset to the high level. Afterwards, the column selection signals CLA, CLB rise to the high level and the bit line pairs are connected to the respective data bus line pairs. Then, the word lines WLA, WLB each rise temporarily and different memory cells in the same column are selected.
The second bit line pair BLB, XBLB and second data bus line pair DBB, XDBB, which are carrying out reading, are driven by the memory cell MC and, as shown, have a slight potential difference .DELTA.V. The signal NSAB, which drives the second sense amp SAB, rises, whereupon the second bit line pair BLB, XBLB and second data bus line pair DBB, XDBB are driven greater and become high level and low level. Meanwhile, the first data bus line pair DBA, XDBA and the first bit line pair BLA, XBLA are driven by the write amp WA; in this example, one bit line BLA is driven greater at the low level. In response to this driving, the second bit line BLB coupled with the parasitic capacity C1 is also driven toward the low level side; in the worst case, the High and Low levels become reversed between the second bit line pair BLB, XBLB. Such a reversal results in the sense amp SAB outputting data which was read in error. The aforementioned erroneous read operation sometimes occurs in the same way when reading a different memory cell in the same column.
Japanese Patent Laid-open Publication No. 4-252494 is a known example which makes note of reducing crosstalk among a plurality of pairs of data bus lines. However, this patent does not indicate the problems with memory having the aforementioned plurality of bit line pairs established for one column.